From:                     Kendra Smith

Sent:                      Wednesday, April 12, 2000 12:20 AM

To:                         M?crosöft Research Tech Talk, Sem. Notice

Cc:                         Kendra Smith

Subject:                 UW-CSE Colloq / 4-20-2000 / Mahlke / HP Labs / Compiler-Directed Synthesis of Hardware Accelerators

UW-CSE Colloq / 4-20-2000 / Mahlke / HP Labs / Compiler-Directed Synthesis of Hardware Accelerators

 

*NOTE* This lecture will be broadcast live via the Internet. See

http://www.cs.washington.edu/news/colloq.info.html for more information.

 

UNIVERSITY OF WASHINGTON

Seattle, Washington 98195

 

Department of Computer Science and Engineering

Box 352350

(206) 543-1695

 

COLLOQUIUM

 

SPEAKER:      Scott Mahlke, Hewlett-Packard Labs

 

TITLE:          Compiler-Directed Synethesis of Hardware Accelerators

         

DATE:           Thursday, April 20, 2000

 

TIME:           3:30 pm

 

PLACE:                   134 Sieg Hall

 

HOST:           Susan Eggers

 

ABSTRACT:

 

An ever larger variety of embedded ASICs is being designed and deployed to

satisfy the explosively growing market for new electronic devices.  Many

of these devices handle demanding multi-media computations.  In many such

ASICs, specialized nonprogrammable hardware accelerators (NPAs) are used

for parts of the application that would run too slowly if implemented in

software on a programmable processor.  Rapid, low-cost design, low

production cost, and high performance are all important in NPA design.  In

order to reduce the design time and design cost, automated design of NPAs

from high-level specifications is becoming increasingly important.  A

principal goal of the HP Labs Program-In-Chip-Out (PICO) project is to

automate the design of NPAs.

 

One of the critical factors in this design process is the width of the

data processed by the application.  The width of the data directly

controls the width of the necessary hardware components and thus the cost

of the NPA.  In most multi-media applications, full 32-bit integer data is

rarely required. Therefore, the cost of the hardware can be substantially

reduced by detecting narrow computations and synthesizing narrow hardware

components.  The PICO synthesis system employs an automatic bitwidth

analysis system to derive the width for each variable, temporary, and

operator within an application.  This information is then used to drive

hardware synthesis to create width-conscious designs of NPAs.  In this

talk, I will first present an overview of the PICO project and the NPA

synthesis system that has been developed.  Second, the bitwidth analysis

system is examined in more depth.  Our approach and someexperiments

demonstrating the effectiveness of the analysis are presented.

 

Refreshments to follow.

 

Email: talk-info@cs.washington.edu

Info: http://www.cs.washington.edu